9月份的 jssc 论文，简单列一下可以关注的部分：
Multiloop High-Power-Supply-Rejection Quadrature Ring Oscillator
基于source-follower结构的delay-cell实现的multi-loop ring oscillator
A High-Speed Fully-Integrated POF Receiver With Large-Area Photo Detectors in 65 nm CMOS
主要是关于super-gm trans-impedance amplifier 和 linear equalizer的介绍
1-1-1 MASH Time-to-Digital ΔΣ Converters With 6ps Resolution and Third-Order Noise-Shaping
TDC中采用的三阶时域噪声整形的方法
A 88-dB DR, 84-dB SNDR Very Low-Power Single Op-Amp Third-Order ΣΔ Modulator
低功耗的ΣΔ modulator的设计，具体的改进的3阶ΣΔ的架构和单运放的实现方式
A Pipelined ADC With Metastability Error Rate < 10-15 Errors/Sample
利用time-interleaving和look-ahead的结构减小比较器的亚稳态导致的BER
Digitally Calibrated 768-kS/s 10-b Minimum-Size SAR ADC Array With Dithering
利用Digitally Calibration减小SAR ADC中的电容阵列的大小
A 12-b, 30-MS/s, 2.95-mW Pipelined ADC Using Single-Stage Class-AB Amplifiers and Deterministic Background Calibration
主要是对于pipelined-adc的功耗的考虑，利用calibration减小对放大器增益的要求，从而可采用单级的class-ab结构，同时控制放大器动态开启进一步降低功耗
A 20-b 40-mV Range Read-Out IC With 50-nV Offset and 0.04% Gain Error for Bridge Transducers
Current-feedback instrumentation amplifier + sc incremental ΔΣ adc的结构，CFIA中的DEM和chopping的方法以减小offset和noise
A 450-mV Single-Fuel-Cell Power Management Unit With Switch-Mode Quasi-V2 Hysteretic Control and Automatic Startup on 0.35- m Standard CMOS Process
在boost变换器中采用Quasi-V2 Hysteretic控制方法，以及启动问题的分析
Cross Feedforward Cascode Compensation for Low-Power Three-Stage Amplifier With Large Capacitive Load
多级放大器中的交叉前馈cascode补偿方法，改善大电容负载下的系统稳定问题