JSSC 2012-11 笔记

11月的JSSC论文,  还是列一下其中的部分内容:

An 80 mV Startup Dual-Mode Boost Converter by Charge-Pumped Pulse Generator and Threshold Voltage Tuned Oscillator With Hot Carrier Injection

利用Charge-pumped pulse generator 实现低压下的启动操作,对oscillator 通过调整阈值的方法改善variation 的影响

A Near-Optimum Dynamic Voltage Scaling (DVS) in 65-nm Energy-Efficient Power Management with Frequency-Based Control (FBC) for SoC System

将功率控制回路与PLL环路结合实现的hybrid control 的方法

A High-PSRR Reconfigurable Class-AB/D Audio Amplifier Driving a Hands-Free/Receiver 2-in-1 Loudspeaker

具体的Class-AB/D 的电路以及其中的voltage tracking common mode reference 的结构

A 10-b Ternary SAR ADC With Quantization Time Information Utilization

具体关于Ternary SAR ADC 结构的分析

A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation

时间交织结构的流水线SAR ADC 以及具体的offset cancellation 的方法

A Low-Energy Crystal-Less Double-FSK Sensor Node Transceiver for Wireless Body-Area Network

主要可以看看关于injection locking DCO的结构

A Leakage-Current-Recycling Phase-Locked Loop in 65 nm CMOS Technology

薄栅PMOS做LPF时的漏电问题,同时利用此漏电流供电给VCO,Divider等

CMOS Circuits to Measure Timing Jitter Using a Self-Referenced Clock and a Cascaded Time Difference Amplifier with Duty-Cycle Compensation

具体的对于片上时域抖动的检测电路的分析

An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC with Resistive DAC

具体的SAR ADC 的结构以及电路中的interpolated sampling,bootstrapping,offset cancel 等

An 11-b 300-MS/s Double-Sampling Pipelined ADC with On-Chip Digital Calibration for Memory Effects

Channel之间 opamp sharing 导致的memory effect 问题,对此的calibration方法

A 1-μW 10-bit 200-kS/s SAR ADC with a Bypass Window for Biomedical Applications

针对Biomedical 的应用,在SAR ADC 中采用 bypass window的方法减小功耗

A 190- W zero-IF GFSK Demodulator with a 4-b Phase-Domain ADC

主要是了解一下关于 phase domain ADC 的结构

2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors

高比特率高熵的真随机数发生器,主要看看和与一般的线性反馈移位寄存结构的伪随机数发生器的差别。