之前曾经贴过Basic Precautions for an Analog Designer 的原文,最近整理以前的工作,顺便把它翻出来,附上简单的翻译。
Basic precautions and tips that an Analog Designer should know.
关于模拟集成电路电路设计须知
1. Minimum channel length of the transistor should be four to five times the minimum feature size of the process. We do it, to make the lambda of the transistor low i.e. the rate of change of Id w.r.t to Vds is low.
晶体管最小沟长为工艺最小特征尺寸的4-5倍,用来减小沟长调制效应
2. Present art of analog design still uses the transistor in the saturation region.So one should always keep Vgs of the Transistor 30% above the Vt.
目前模拟集成电路设计仍然是使晶体管工作在饱和区,故应使Vgs大于Vt约30%
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