之前曾经贴过Basic Precautions for an Analog Designer 的原文，最近整理以前的工作，顺便把它翻出来，附上简单的翻译。
Basic precautions and tips that an Analog Designer should know.
1. Minimum channel length of the transistor should be four to five times the minimum feature size of the process. We do it, to make the lambda of the transistor low i.e. the rate of change of Id w.r.t to Vds is low.
2. Present art of analog design still uses the transistor in the saturation region.So one should always keep Vgs of the Transistor 30% above the Vt.
3. One should always split the big transistor into small transistors having width or length feature size < or = 15um.
4. W/L Ratio of transistors of the mirror circuit should be less than or equal to 5, to ensure the proper matching of the transistors in the layout. Otherwise, it results to the Systamatic Offset in the circuit.
5. One should make all the required pins in the schmetic before generating the layout view. Because it’s diffcult to add a pin in the layout view. All IO pins should be a metal2 pins whereas Vdd and Ground should be metal1 pins
在原理路中画出所有的管脚（pin），之后才作layout。因为在layout中增加一个pin是比较困难的。所有的IO pin应该用metal2 pin，Vdd和GND用metal1 pin
6. One should first simulate the circuit with the typical model parameters of the devices. Since Vt of the trasistor can be anything between Vt(Typical) -/+ 20%. So we check our circuit for the extreme cases i.e. Vt+20%, Vt-20%. A transistor having Vt-20% is called a fast transistor and transistor having Vt+20% is called slow transistor. It’s just a way to differentiate them. So with these fast and slow transistor models we make four combination called nfpf, nfps, nspf, nsps, which are known as process corners. Now, once we are satisfied with the circuit performance with typical models than we check it in different process corners, to take the process variation into account. Vt is just one example of the process variation there are others parameter too.
首先先用tt模型做电路仿真。考虑Vt有+20% (slow)和-20% (fast)的变化,需要对工艺角考虑，FF，SS，FS，SF。除Vt，其他工艺参数也会有变化
7. Its thumb rule that poly resistance has a 20% process variation whereas well resistance has got 10%. But the poly resistance has got lower temperature coefficent and lower Sheet Resistance than well resistance So we choose the resistance type depending upon the requirments. Poly Capacitance has got a process variation of 10%.
8. One should also check the circuit performance with the temperature variation. We usuly do it for the range of -40C to 85C.
9. One should take the parasitic capacitance into account wherever one is making an overlap with metal layers or wells.
10. In Layout, all transistors should be placed in one direction, to provide the same environment to all the transistors.
11. One should place all transistor in layout with a due care to the pin position before start routing them.
12. One should always use the Metal 1 for horizontal routing and Metal 2 for the vertical routing as far as possible.
13. One should never use POLY as routing layer when the interconnects carries a current. One can have a short gate connection using poly.
14. One should try to avoid running metal over poly gate. As this cause to increase in parasitic capacitance.
15. Current in all the transistor and resistor part should flow in the same direction.
16. One should do the Power(Vdd & Gnd) routing in top layer metal (metal5 only). Because Top layer metals are usually thicker and wider and so has low resistance.
17. One should always merge drain and source of transistor (of same type) connected together.
18. To minimize the process variation in the Resistor value one should always take the resistor’s width three to four times of the default value. we do it to decrease the value of differential of R(L)
19. One should cover the resistance with metal layer, to avoid the damaged during the wafer level testing.
20. One should always make a Common Centroid structure for the matched transistor in the layout.
* Each differential pair transistor should be divide into four transistors and should be placed in two rows common centroid structure.
* One may use the the linear common centroid structure for the current mirror circuit.
21. It’s advisiable to put a dummy layers around the resistance and the capacitance to avoid the erosion at the time of etching.
22. One should always have a Guard Ring arround the differential pair.
23. Always put a Guard Ring arround the N-well and P-well.
24. Thumb rule for the metal current density is 0.8mA/um. It’s larger for the top most metal layer.
25. To avoid the Latchup, one should always make the PN junction reverse biased i.e. In NWELL should be connected to positive power supply (Vdd) and PWELL should be connected to negative power supply (Gnd). Designers do it to make the leakage current small.
26. It’s always a good practice to use a infotext layer to put the name of the device on the top of it in layout and have a netname for every nets in schematic. Designer should put the pin name on the top of the pin with same metaltxt layer because hercuels takes the netname from metaltxt only whereas Diva takes from the pin-name.
27. Cadence SPICE simulator take vdd! & gnd! as a global Vdd and Gnd net i.e. any net ending with ‘ !’ is considered as a global net..
28. Transistor Equation:
Gm=square root of(2Id*beta)