简单记录一下六月份 JSSC 的几篇论文

A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques

Adaptive tracking averaging 的方法和 filtered-DAC 的结构

An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers

低压下采用 open-loop residue amplifier 和 interpolation 的结构

A High-Voltage Class-D Power Amplifier With Switching Frequency Regulation for Improved High-Efficiency Output Power Range

在Class-D 电路中采用频率调节方式改善效率的分析

Design of On-Chip Gate Drivers With Power-Efficient High-Speed Level Shifting and Dynamic Timing Control for High-Voltage Synchronous Switching Power Converters

关于 capacitively coupled level shifter 和 dynamically controlled level shifter 的结构