JSSC 2012-08 笔记


8月份的jssc论文主要选取的是2011年的CICC会议上的论文,这里大致列一下里面的部分内容:

Complete SOC Transceiver in 0.18 um CMOS Using Q-Enhanced Filtering, Sub-Sampling and Injection Locking

低功耗的考虑,具体在设计中采用Q-Enhanced Filtering, Sub-Sampling 以及Injection Locking等

A Transformer-Based Broadband Front-End Combo in Standard CMOS

集成的transformer,以包括T/R switch,balun和impedance matching的功能

A 1.9 GHz CMOS Power Amplifier with Embedded Linearizer to Compensate AM-PM Distortion

PA设计中采用的基于pre-distortion的的线性化技术

A 16-Gb/s Backplane Transceiver with 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology

利用Dynamic Adaptation of Voltage Offset and Timing Drifts 补偿电源和温度的变化

0.16-0.25 pJ/bit, 8 Gb/s Near-Threshold Serial Link Receiver With Super-Harmonic Injection-Locking

利用亚阈值的工作以及data-slicing的结构提升能量效率的方法

A40-mW 7-bit 2.2-GS/s Time-Interleaved Subranging CMOS ADC for Low-Power Gigabit Wireless Communications

采用Time-splitting sub-range的结构提升单个adc通路的速度

A 1-1-1-1 MASH Delta-Sigma Modulator With Dynamic Comparator-Based OTAs

在开关电容积分器中利用Dynamic Comparator-Based OTAs结构

A 16 MHz BW 75 dB DR CT ΔΣ ADC Compensated for More Than One Cycle Excess Loop Delay

关于1.5 clock cycle 的excess loop delay的补偿方法

A 0.5-V, 440u- W Frequency Synthesizer for Implantable Medical Devices

低压低功耗的频率综合器的设计,动态的阈值控制等方法

A Dither-Less All Digital PLL for Cellular Transmitters

包括2D vernier time-to-digital converter和dither-less DCO, 以及系统中大量的digital calibration

A 60 mW Class-G Stereo Headphone Driver for Portable Battery-Powered Devices

高阶前馈环路以提高psrr,以及输出级的Class-AB/B的结构改善效率

A Switched-Inductor Integrated Voltage Regulator with Nonlinear Feedback and Network-on-Chip Load in 45 nm SOI

Unlatched PWM控制以实现快速的动态响应,减小所需的输出电容

Practical Considerations for a Digital Inductive-Switching DC/DC Converter With Direct Battery Connect in Deep Sub-Micron CMOS

数字控制方式实现,ΣΔ modulator 和z域实现的补偿等


版权声明: 本站文章版权所有,转载须以超链接形式标明文章原始出处和版权信息。

JSSC 2012-08 笔记》上有1条评论

发表评论

电子邮件地址不会被公开。 必填项已用*标注