JSSC 2011-9 笔记

9月份的JSSC, 简单列一下觉得可以了解的内容:

Transmitter Linearization by Beamforming


A 0.46-mm2 4-dB NF Unified Receiver Front-End for Full-Band Mobile TV in 65-nm CMOS

利用 gain-boosting current-balancing balun-LNA ,current-reuse mixer-low-pass-filter 和 direct injection-locked 4-/8-phase LO generator 来提升性能,减小功耗和面积

A 90-nm CMOS Threshold-Compensated RF Energy Harvester


Frequency-Hopped Quadrature Frequency Synthesizer in 0.13-um Technology

基于sub-harmonic injection-locking 的结构频率综合器

Frequency Tuning of Wide Temperature Range CMOS LC VCOs

对LC VCO的温度特性的分析

Crosstalk-Aware PWM-Based On-Chip Links With Self-Calibration in 65 nm CMOS


A Single-Loop SS-LMS Algorithm With Single-Ended Integrating DFE Receiver for Multi-Drop DRAM Interface


A 5-GHz Direct Digital Frequency Synthesizer Using an Analog-Sine-Mapping Technique in 0.35-um SiGe BiCMOS

利用TSC (triangle-to-sin converter) 将相位数据转换为正弦波的方法

A 240-frames/s 2.1-Mpixel CMOS Image Sensor With Column-Shared Cyclic ADCs

主要是其中的 cyclic ADC 的具体电路设计

A 0.8 ps DNL Time-to-Digital Converter With 250 MHz Event Rate in 65 nm CMOS for Time-Mode-Based ΣΔ Modulator

利用 PWM 和 TDC(Time-to-Digital Converter)替换 ΣΔ ADC 中的多比特量化器的结构

A Single-Temperature Trimming Technique for MOS-Input Operational Amplifiers Achieving 0.33 V/ C Offset Drift


A 90–240 MHz Hysteretic Controlled DC-DC Buck Converter With Digital Phase Locked Loop Synchronization

关于 Hysteretic Controlled DC-DC 变换器的实现,以数字 PLL 实现的同步结构

Design Techniques for Fully Integrated Switched-Capacitor DC-DC Converters

关于开关电容 dc-dc 变换器(电荷泵)的详细分析

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