8月的JSSC的内容基本是来源于2010年的CICC （IEEE Custom Integrated Circuits Conference） 会议上的论文， 简单列一下可以关注的部分：
A 4-Port-Inductor-Based VCO Coupling Method for Phase Noise Reduction
基于 4-port inductor coupling 结构的VCO，此结构振荡器的工作原理和具体相位噪声的分析
A 475 mV, 4.9 GHz Enhanced Swing Differential Colpitts VCO With Phase Noise of -136 dBc/Hz at a 3 MHz Offset Frequency
利用ESDC-VCO （Enhanced Swing Differential Colpitts VCO）的结构，实现的电源电压的VC
Design and Analysis of Varactor-Less Interpolative-Phase-Tuning Millimeter-Wave LC Oscillators with Multiphase Outputs
利用 interpolative-phase-tuning (IPT) 方法来实现频率调谐，实现的Varactor-Less 环振
An Inside Body Power and Bidirectional Data Transfer IC Module Pair
主要还是里面的passive MOS ac-dc converter 的设计
A 6-Gb/s MIMO Crosstalk Cancellation Scheme for High-Speed I/Os
采用的多入多出连续时间均衡器（multiple-input multiple-output continuous-time equalizer）的低功耗的串扰消除crosstalk mitigation 方法
Fully Digital Transmit Equalizer With Dynamic Impedance Modulation
与传统的恒定阻抗方式不同，这里用dynamic impedance modulation 的方法实现Transmit pre-emphasis 预加重电路
A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked LoopWith Bandwidth Tracking
采用数字滤波器作为锁相环的环路滤波器的设计，并以此减小DCO的相位噪声
A 550-uW 10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error Correction
SAR ADC 的设计，主要是关于Multistep Addition-Only Digital Error Correction （ADEC）的方法
SHA-Less Pipelined ADC With In Situ Background Clock-Skew Calibration
SHA-less pipelined ADC中，利用digital skew calibration结构来消除timing error的方法
Exploiting Combinatorial Redundancy for Offset Calibration in Flash ADCs
采用statistical element selection (SES) 方法的offset-calibrated comparator的设计
A 5-MHz 11-Bit Self-Oscillating ΣΔ Modulator With a Delay-Based Phase Shifter in 0.025 mm2
噪声整形与PWM结合的Sigma-Delta modulator的设计
A 5-MHz 91% Peak-Power-Efficiency Buck Regulator With Auto-Selectable Peak- and Valley-Current Control
采用auto-selectable peak- and valley-current control (ASPVCC) 结构实现的高开关频率的dc-dc converter.
Fully-Integrated On-Chip DC-DC Converter With a 450X Output Range
针对 DVS ( dynamic voltage scaling ) 的 dc-dc 变换器的设计，主要是通过输出电流的检测以使变换器在不同模式下工作