JSSC 2011-6 笔记

6月份的JSSC, 简单列一下觉得可以了解的内容:

Analysis and Design of Small-Signal Polar Transmitters for Cellular Applications

关于GSM/EDGE/WCMA应用的direct-modulated and small-signal polar transmitters,主要还是 Direct-modulated PLL 的分析和关于Polar loop 分析

Analysis and Design of D-Band Injection-Locked Frequency Dividers

在D-band (110-170 GHz)频率范围的 injection-locked frequency dividers (ILFDs),具体的 distributed-LC technique方法的分析:输入频率, 锁定范围和设计考量

A Wideband Millimeter-Wave Frequency Synthesis Architecture Using Multi-Order Harmonic-Synthesis and Variable N-Push Frequency Multiplication

主要看的还是其中的系统结构 — two-step multi-order harmonic generation of a low frequency phase-locked signal to generate wide-band millimeter-wave frequency

A 10.2 Mbps Pulse Harmonic Modulation Based Transceiver for Implantable Medical Devices

基于pulse harmonic modulation (PHM) 的低功耗的无线收发机的设计

A Frequency Synthesizer With Optimally Coupled QVCO and Harmonic-Rejection SSBmixer for Multi-Standard Wireless Receiver

应用于multi-standard无线通信接收机中的宽带小数频率综合器(fractional-N frequency synthesizer)的设计,采用新型的phase shifter 结构的Quadrature VCO来改善相位噪声和振荡稳定性;结合 harmonic rejection和single-sideband mixing的方法的harmonic rejection SSB 混频器来抑制有害的边带和spur

Low-Power CMOS Equalizer Design for 20-Gb/s Systems

采用的power scaling的方法和半速率的DFE(decision-feedback equalizer)的结构来实现速度-功耗的折中

7.4 Gb/s 6.8 mW Source Synchronous Receiver in 65 nm CMOS

可以耐受高频抖动(high frequency jitter)的接收机的结构,通过发送端pulsed clock forward的方法以跟踪correlated jitter来改善系统的jitter tolerance

A Charge-Domain Auto- and Cross-Correlation Based Data Synchronization Scheme With Power- and Area-Efficient PLL for Impulse Radio UWB Receiver

关于离散时间电荷域的impulse radio ultra-wideband (IR-UWB) receiver的设计,这里还是看一下里面关于 dual charge-pump PLL的设计

A 10-bit, 40-MS/s, 1.21 mW Pipelined SAR ADC Using Single-Ended 1.5-bit/cycle Conversion Technique

10-bit 的SAR ADC 划分为4-bit (第一级) 和 6-bit (第二级) SAR ADC,采用这样的两级Pipeline的结构来减少电容,在第一级采用了single-ended 1.5bit/cycle 的方法来消除比较器的失调,在第二级采用了 pseudo C-2C 结构来减小余数放大器的负载电容

A 14 bit 200 MS/s DAC With SFDR 78 dBc, IM3 83 dBc and NSD 163 dBm/Hz Across the Whole Nyquist Band Enabled by Dynamic-Mismatch Mapping

Current-steering DAC 设计,主要在与里面的 dynamic mismatch mapping (DMM)  的数字校准的方法

A 10-MHz Green-Mode Automatic Reconfigurable Switching Converter for DVS-Enabled VLSI Systems

DVS 应用的 dc-dc converter 的设计,主要还是里面的 adaptive power transistor sizing 的方法, iL-assisted single-bound hysteresis controller (SBHC) 的结构,以及 adaptive frequency compensator (AFC) 的方法

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