对于中国主要的 Fabless 公司来说，挥手告别2007并不是一件非常轻松的事。回顾过去的一年，这些一直活跃在各大主流媒体的 IC 设计公司交出的答卷可以说是相当不尽人意：2006年评出的中国十大 Fab l

PDF 摘要：
第二部分：调制和复用技术
作者： Daniel M. Dobkin
幅度、频率和相位均不变的周期信号—连续波 (CW) 信号—除了它的存在之外…

PDF 摘要：
起初，并没有考虑将运算放大器 (op amps) 用于 RF 设计。然而，随着速度更快的、更新的器件的出现，已使运算放大器成为某些应用中的上佳选择。RF 设计人员…

This paper is intended to eliminate the confusion around electrostatic discharge (ESD) protection architectures so that designers can confidently take the next step toward designing more reliable systems.

“Relationship between frequency response and settling time of operational amplifiers”
Kamath, BYT; Meyer, RG; Gray, PR.
IEEE JSSC’74
“Analysis of the settling behavior of an operational amplifier”
Chuang, C.T.;
IEEE JSSC’82

Metal density refers to the ratio of metal features to open features for a given metal mask. This is primarily a requirement for the Wafer Fab metal etch process, but can have implications for plasma damage …

THE PDF WHICH GIVES A CLEAR NOTE OF CONCEPT OF POLES AND ZEROS.

This article explains the purpose of the low-pass filter components in Class-D amplifiers and how to calculate their values

One trick.
Place voltage source with AC magnitude = 1V in series with output between output and load. Do AC analysys and measure current flowing though output terminal – Iout.
The output impedance Zout=1V/Iout.

Why we have to satisfy metal density in layout.

some thing about the opamp’s noise performance

The paper “Determination of stability using return ratios in balanced fully differential feedback circuits” by Paul Hurst, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-11: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 42, NO. 12, DECEMBER 1995

The first in a series of articles from the “Distortion in power amplifiers” series originally published in Electronics World examines the sources of distortion in power amplifiers.

the Top RFDesignLine articles of 2007

some discussion about drop-out voltage in LDO

how to simulate the AC performance of LDO

Effect of DNWELL on substrate noise

目前，中国本土 IC 设计公司有400多家，覆盖着多个产业领域，尤其在手机、MP3、PMP、HDTV 等消费电子领域本土 IC 设计公司迅速成长，与国际 IC 巨头的差距越来越小。在08年即将来临之际，电子工程专

Jitter, Noise, and Signal Integrity at High Speed, is a basic and high-level introduction to terminology, definitions, and concepts concerning jitter, noise, signal integrity, bit error rate, and working mechanisms for communication link systems.

Power Management DesignLine’s most popularly read technical articles for 2007.
Subject-wise, buck regulators and battery charging articles with a particular connection to solar energy are important to you

M5,M6 is used to reduce the systematic offset and to increase the current mirror accuracy

Deskew PLLs : outputs and input have same phase, limited freq selection
Clock generator PLLs : generate a wide range of output freq
Spread Spectrum PLLs : similiar to Clock generator PLLs with EMI reduction of peak energy
…

some papers about PLL

the phd. thesis of Rincon-Mora and his ieee paper in “current efficient , low voltage , low drop out regulators”.

papers for DC-DC converter

Here are the top ten most popular audio design-related articles for the year. This list will be updated every week through the end of the year.

Clock jitter can make even a perfect analog/digital converter (ADC) perform poorly; understand its causes and how to assess accurately

This segment is a discussion of the sources of jitter and amplitude noise.

This paper describes common sources of pop-and-click artifacts in PC audio systems and presents solutions for minimizing them.

there are basically two ways to do it: one is in layout, use multi-finger, and the other is in design by maximizing the overdriven voltage of both MOSFET need to be matched

Weak and moderate inversion level is optimal region for amplifier. Strong inversion for diff pair is used in Gm-C filter where linearity in attention.

Jitter, Noise, and Signal Integrity at High Speed, is a basic and high-level introduction to terminology, definitions, and concepts concerning jitter, noise, signal integrity, bit error rate, and working mechanisms for communication link systems

EDA tools can assess the first-order jitter and other performance attributes of the phase-lock loop, a critical block in many systems