简单列一下六月份 JSSC 的几篇论文

A 2.2 GHz −242 dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture

ADC 结构提高 phase digitalization的 resolution 从而改善相位噪声

A 4 Bit Continuous-Time ΣΔ Modulator With Fully Digital Quantization Noise Reduction Algorithm Employing a 7 Bit Quantizer

对 MASH 结构的CT-SDM, 将量化器的低三位用作quantization noise reduction

A SAR ADC With a MOSCAP-DAC

主要是基于 charge-sharing ADC 的结构

A 2.4 mA Quiescent Current, 1 W Output Power Class-D Audio Amplifier With Feed-Forward PWM-Intermodulated- Distortion Reduction

利用 replica circuit 方式的前馈结构来改善 pwm-intermodulated-distortion