JSSC 2014-12 笔记

列一下12月的两篇 JSSC 论文

A 10/30 MHz Fast Reference-Tracking Buck Converter With DDA-Based Type-III Compensator

利用 differential difference amplifier 实现的3型补偿以减小面积

A Fractional-N Divider-Less Phase-Locked Loop With a Sub-sampling Phase Detector

使用 Digital PWM 实现的小数工作方式

JSSC 2014-11 笔记

继续关于11月的 JSSC 论文的部分内容:

Integrated Class-D Audio Amplifier With 95% Efficiency and 105 dB SNR

采用前馈的ADC路径扩展Loop Filter 的工作范围,反馈滤波路径减小信号的干扰

Low Power Design Techniques for Single-Bit Audio Continuous-Time Delta Sigma ADCs Using FIR Feedback

连续时间 Sigma-Delta ADC 中采用 FIR DAC 的具体分析

A LDO Regulator With Weighted Current Feedback Technique for 0.47 nF–10 nF Capacitive Load

利用 Negative current feedback 方式避免右半平面极点的方法

A 32 nm Embedded, Fully-Digital, Phase-Locked Low Dropout Regulator for Fine Grained Power Management in Digital Circuits

基于 phase locked 结构的数字实现的 LDO 的设计

JSSC 2014-10 笔记

简单的列一下十月份的几篇 JSSC 论文

Design Techniques for Continuous-Time ΔΣ Modulators With Embedded Active Filtering

针对应用中的干扰问题,在连续时间 sigma-delta modulator 环路中加入低通滤波器的方法的分析

A Fully Self-Contained Logarithmic Closed-Loop Deep Brain Stimulation SoC With Wireless Telemetry and Wireless Power Management

关于其中的 Logarithmic processing 和logarithmic ADC 的设计考虑

A Reconfigurable 40-to-67 dB SNR, 50-to-6400Hz Frame-Rate, Column-Parallel Readout IC for Capacitive Touch-Screen Panels

其中的Incremental sigma-delta ADC 的设计以及系统噪声的分析

JSSC 2014-09 笔记

九月份的几篇 JSSC 论文, 还是简单的记录一下:

A 2 GS/s Frequency-Folded ADC-Based Broadband Sampling Receiver

将频率折到 mixing LO谐波从而使用低速的sub-ADC实现设计

A Compact and Low-Power Fractionally Injection-Locked Quadrature Frequency Synthesizer Using a Self-Synchronized Gating Injection Technique for Software-Defined Radios

Core PLL 加上 fractional injection locked frequency divider 的结构

A Micro Inertial Energy Harvesting Platform With Self-Supplied Power Management Circuit for Autonomous Wireless Sensor Nodes

其中的power-management 部分的考虑


JSSC 2014-08 笔记

简单的列一下八月份的 JSSC 的部分内容:

A Fully-Integrated 71 nW CMOS Temperature Sensor for Low Power Wireless Sensor Nodes


Sampling Circuits That Break the kT/C Thermal Noise Limit


A 40 nm Fully Integrated 82 mW Stereo Headphone Module for Mobile Applications

关于其中的 power distribution的考虑

A 7.1 mW 1 GS/s ADC With 48 dB SNDR at Nyquist Rate

在两级 pipelined ADC 设计中考虑 residue gain error, offset, nonlinearity 的问题

An 8 Bit 4 GS/s 120 mW CMOS ADC

采用 pipelined time interleaved 结构和 timing mismatch detection的方法