JSSC 2015-07 笔记

列一下7月的两篇 JSSC 论文

Area Efficient Integrated Gate Drivers Based on High-Voltage Charge Storing

具体的 gate driver 的电压的 bootstrap 的结构

A 12 b 53 mW 195 MS/s Pipeline ADC with 82 dB SFDR Using Split-ADC Calibration

对 residue amplifier 的 settling error 的 calibration 方法

A 600 μA 32 kHz Input 960 MHz Output CP-PLL With 530 ps Integrated Jitter in 28 nm FD-SOI Process

采用 Dual-loop filter 对 resistor noise 的改善

JSSC 2015-06 笔记

简单记录一下六月份 JSSC 的几篇论文

A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques

Adaptive tracking averaging 的方法和 filtered-DAC 的结构

An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers

低压下采用 open-loop residue amplifier 和 interpolation 的结构

A High-Voltage Class-D Power Amplifier With Switching Frequency Regulation for Improved High-Efficiency Output Power Range

在Class-D 电路中采用频率调节方式改善效率的分析

Design of On-Chip Gate Drivers With Power-Efficient High-Speed Level Shifting and Dynamic Timing Control for High-Voltage Synchronous Switching Power Converters

关于 capacitively coupled level shifter 和 dynamically controlled level shifter 的结构




JSSC 2015-05 笔记

简单列一下五月份的 JSSC 的几篇论文

A 0.22 psrms Integrated Noise 15 MHz Bandwidth Fourth-Order ΔΣ Time-to-Digital Converter Using Time-Domain Error-Feedback Filter

关于其中的 MASH 结构的 TDC 具体实现方式

Digitally Controlled Leakage-Based Oscillator and Fast Relocking MDLL for Ultra Low Power Sensor Platform

对于 leakage based oscillator 的设计分析

A VO-Hopping Reconfigurable RGB LED Driver With ΔVO Automatic Detection and Predictive Peak Current Control

Burst mode peak current controller 和 adaptive off timer 的设计

JSSC 2015-04 笔记

4月份的 JSSC 的几篇论文,还是简单列一下

A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC

在小数分频部分利用 digital-to-time converter 来消除 delta-sigma 调制器的量化噪声的考虑.

A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method


A 23 mW, 73 dB Dynamic Range, 80 MHz BW Continuous-Time Delta-Sigma Modulator in 20 nm CMOS


High Frequency Buck Converter Design Using Time-Based Control Techniques

对于buck converter的具体的时域控制方法的介绍