JSSC 2016-10 笔记

贴一下十月份的 JSSC 中的几篇论文

A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers

对 residue amplifier 采用线性化的开环放大器的结构的考虑

A 12-bit 104 MS/s SAR ADC in 28 nm CMOS for Digitally-Assisted Wireless Transmitters

关于 power-on calibration 对CDAC的实配的校正的方法

A Load-Adaptive Class-G Headphone Amplifier With Supply-Rejection Bandwidth Enhancement Technique


An Analog Front-End for a Multifunction Sensor Employing a Weak-Inversion Biasing Technique With 26 nVrms, 25 aCrms, and 19 fArms Input-Referred Noise


A 1 A, Dual-Inductor 4-Output Buck Converter With 20 MHz/100 MHz Dual-Frequency Switching and Integrated Output Filters in 65 nm CMOS

关于 dual-frequency dual-inductor multi-output buck converter 的设计

JSSC 2016-09 笔记

简单的记录一下九月份 JSSC 的几篇论文

Integration Trends in Monolithic Power ICs: Application and Technology Challenges

关于 BCD 工艺和集成电源模块如电荷泵, 开关电源等的回顾

A 110 nW Resistive Frequency Locked On-Chip Oscillator with 34.3 ppm/C Temperature Stability for System-on-Chip Designs

在RC弛豫振荡器中加入VCO实现的无比较器的结构, 以去除比较器带来功耗和温度相关的延时

A 5.6 nV/Hz Chopper Operational Amplifier Achieving a 0.5 µV Maximum Offset Over Rail-to-Rail Input Range with Adaptive Clock Boosting Technique

电路中具体的频率补偿的方法, 针对ripple 问题的auto correction feedback , 以及关于adaptive clock boosting 的方法

JSSC 2016-08 笔记

简单列一下八月份的 JSSC 的两篇论文

A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC

关于 Assisted ADC 和 Main ADC 的实现方式,以及 dynamic gain-boosted pre-amplifier

A 7.2 mW 75.3 dB SNDR 10 MHz BW CT Delta-Sigma Modulator Using GmC-Based Noise-Shaped Quantizer and Digital Integrator

主要是考虑将 dual-slop adc 的 reset 相位去掉从而得到 noise-shaped integrating quantizer

JSSC 2016-07 笔记

贴一下七月份的 JSSC 中的几篇论文

A 106 dB A-Weighted DR Low-Power Continuous-Time ΣΔ Modulator for MEMS Microphones

SDM 中 resonator 位置的选择,以及 excess loop delay 的考虑

Design of Continuous-Time ΔΣ Modulators With Dual Switched-Capacitor Return-to-Zero DACs

由 CT SDM 中 jitter 问题而采用的 SC DAC 结构对系统的线性度和 anti-aliasing 特性的影响

A 13.2 b Optical Proximity Sensor System With 130 klx Ambient Light Rejection Capable of Heart Rate and Blood Oximetry Monitoring

关于其中的 coarse/fine dc compensation 的方法

JSSC 2016-06 笔记

简单列一下六月份 JSSC 的几篇论文

A 2.2 GHz 242 dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture

ADC 结构提高 phase digitalization的 resolution 从而改善相位噪声

A 4 Bit Continuous-Time ΣΔ Modulator With Fully Digital Quantization Noise Reduction Algorithm Employing a 7 Bit Quantizer

对 MASH 结构的CT-SDM, 将量化器的低三位用作quantization noise reduction


主要是基于 charge-sharing ADC 的结构

A 2.4 mA Quiescent Current, 1 W Output Power Class-D Audio Amplifier With Feed-Forward PWM-Intermodulated- Distortion Reduction

利用 replica circuit 方式的前馈结构来改善 pwm-intermodulated-distortion

JSSC 2016-05 笔记

简单列一下五月份的 JSSC 的两篇论文

An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS

结合 Subranging Pipeline SAR 的结构,以及 offset calibration 和 error decision correction 的方法

A Continuous-Time Delta-Sigma Modulator Using ELD-Compensation-Embedded SAB and DWA-Inherent Time-Domain Quantizer

利用 single-amplifier-biquad 结构的三阶CT-SDM 减少所需的放大器,同时亦包含 excess-loop-delay 的补偿