JSSC 2014-10 笔记

简单的列一下十月份的几篇 JSSC 论文

Design Techniques for Continuous-Time ΔΣ Modulators With Embedded Active Filtering

针对应用中的干扰问题,在连续时间 sigma-delta modulator 环路中加入低通滤波器的方法的分析

A Fully Self-Contained Logarithmic Closed-Loop Deep Brain Stimulation SoC With Wireless Telemetry and Wireless Power Management

关于其中的 Logarithmic processing 和logarithmic ADC 的设计考虑

A Reconfigurable 40-to-67 dB SNR, 50-to-6400Hz Frame-Rate, Column-Parallel Readout IC for Capacitive Touch-Screen Panels

其中的Incremental sigma-delta ADC 的设计以及系统噪声的分析

JSSC 2014-09 笔记

九月份的几篇 JSSC 论文, 还是简单的记录一下:

A 2 GS/s Frequency-Folded ADC-Based Broadband Sampling Receiver

将频率折到 mixing LO谐波从而使用低速的sub-ADC实现设计

A Compact and Low-Power Fractionally Injection-Locked Quadrature Frequency Synthesizer Using a Self-Synchronized Gating Injection Technique for Software-Defined Radios

Core PLL 加上 fractional injection locked frequency divider 的结构

A Micro Inertial Energy Harvesting Platform With Self-Supplied Power Management Circuit for Autonomous Wireless Sensor Nodes

其中的power-management 部分的考虑


JSSC 2014-08 笔记

简单的列一下八月份的 JSSC 的部分内容:

A Fully-Integrated 71 nW CMOS Temperature Sensor for Low Power Wireless Sensor Nodes


Sampling Circuits That Break the kT/C Thermal Noise Limit


A 40 nm Fully Integrated 82 mW Stereo Headphone Module for Mobile Applications

关于其中的 power distribution的考虑

A 7.1 mW 1 GS/s ADC With 48 dB SNDR at Nyquist Rate

在两级 pipelined ADC 设计中考虑 residue gain error, offset, nonlinearity 的问题

An 8 Bit 4 GS/s 120 mW CMOS ADC

采用 pipelined time interleaved 结构和 timing mismatch detection的方法


JSSC 2014-07 笔记

2014年7月的部分 JSSC 论文的记录:

Design and Analysis of a High-Efficiency High-Voltage Class-D Power Output Stage

主要是高压部分设计的考虑以及采用的floating voltage regulation 的方法

A Filtering ΔΣ ADC for LTE and Beyond

将 sigma-delta ADC 置于 channel select filter 中的设计

A 0.039 mm2 Inverter-Based 1.82 mW 68.6 dB-SNDR 10 MHz-BW CT-ΣΔ-ADC in 65 nm CMOS Using Power- and Area-Efficient Design Techniques

关于 CT SDM 中采用的 FIR DAC 和 IIR quantizer 的问题

0.3–4.3 GHz Frequency-Accurate Fractional- Frequency Synthesizer With Integrated VCO and Nested Mixed-Radix Digital -ΔΣ Modulator-Based Divider Controller

关于结合programmable modulus 和 power-of-2 modulus 改善accuracy 和 spur 的问题