JSSC 2016-07 笔记

贴一下七月份的 JSSC 中的几篇论文

A 106 dB A-Weighted DR Low-Power Continuous-Time ΣΔ Modulator for MEMS Microphones

SDM 中 resonator 位置的选择,以及 excess loop delay 的考虑

Design of Continuous-Time ΔΣ Modulators With Dual Switched-Capacitor Return-to-Zero DACs

由 CT SDM 中 jitter 问题而采用的 SC DAC 结构对系统的线性度和 anti-aliasing 特性的影响

A 13.2 b Optical Proximity Sensor System With 130 klx Ambient Light Rejection Capable of Heart Rate and Blood Oximetry Monitoring

关于其中的 coarse/fine dc compensation 的方法

JSSC 2016-06 笔记

简单列一下六月份 JSSC 的几篇论文

A 2.2 GHz 242 dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture

ADC 结构提高 phase digitalization的 resolution 从而改善相位噪声

A 4 Bit Continuous-Time ΣΔ Modulator With Fully Digital Quantization Noise Reduction Algorithm Employing a 7 Bit Quantizer

对 MASH 结构的CT-SDM, 将量化器的低三位用作quantization noise reduction

A SAR ADC With a MOSCAP-DAC

主要是基于 charge-sharing ADC 的结构

A 2.4 mA Quiescent Current, 1 W Output Power Class-D Audio Amplifier With Feed-Forward PWM-Intermodulated- Distortion Reduction

利用 replica circuit 方式的前馈结构来改善 pwm-intermodulated-distortion

JSSC 2016-05 笔记

简单列一下五月份的 JSSC 的两篇论文

An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS

结合 Subranging Pipeline SAR 的结构,以及 offset calibration 和 error decision correction 的方法

A Continuous-Time Delta-Sigma Modulator Using ELD-Compensation-Embedded SAB and DWA-Inherent Time-Domain Quantizer

利用 single-amplifier-biquad 结构的三阶CT-SDM 减少所需的放大器,同时亦包含 excess-loop-delay 的补偿

JSSC 2016-04 笔记

简单的记录一下四月份 JSSC 的两篇论文

A 10/20/30/40 MHz Feedforward FIR DAC Continuous-Time ΔΣ ADC With Robust Blocker Performance for Radio Receivers

连续时间 SDM,关于 clock jitter 和 FIR DAC 的问题

A 3–10 fJ/conv-step Error-Shaping Alias-Free Continuous-Time ADC

类似 integrator + delta encoder 的结构

JSSC 2016-03 笔记

贴一下2016年3月份的几篇 JSSC 论文

A 69 dB SNDR, 25 MHz BW, 800 MS/s Continuous-Time Bandpass ΔΣ Modulator Using a Duty-Cycle-Controlled DAC for Low Power and Reconfigurability

连续时间带通 SDM , 关于中心频率的调整办法

A Constant Energy-Per-Cycle Ring Oscillator Over a Wide Frequency Range for Wireless Sensor Nodes

主要针对 Ring Oscillator 中的电压转换速度和短路电流的问题

Dual-Mode Low-Drop-Out Regulator/Power GateWith Linear and On–Off Conduction for Microprocessor Core On-Die Supply Voltages in 14 nm

Digital Power Gate 和 Analog LDO 两种工作方式, 以及环路的补偿方法

JSSC 2016-02 笔记

简单列一下二月份 JSSC 的几篇论文

A 2.02–5.16 fJ/Conversion Step 10 Bit Hybrid Coarse-Fine SAR ADC With Time-Domain Quantizer in 90 nm CMOS

7-bit coarse SAR ADC + 3.5bit TDC 的方法,考虑功耗电压问题,vcm-based switching 和 double-bootstrapped S/H 的结构

A Compact First-Order ΣΔ Modulator for Analog High-Volume Testing of Complex System-on-Chips in a 14 nm Tri-Gate Digital CMOS Process

Inverter based 结构, 加入 dither 的方法和考虑共模抑制问题而加入的 time-multiplexed pseudo-differential operation

Variation-Tolerant Quick-Start-Up CMOS Crystal Oscillator With Chirp Injection and Negative Resistance Booster

关于晶振启动时间的分析和考虑

A Successive-Approximation Switched-Capacitor DC–DC Converter With Resolution of VIN/2N for a Wide Range of Input and Output Voltages

采用级联 1/2 SC converter 的结构 + SAR logic